This invention relates to testing integrated circuit devices using an algorithm which adjusts a parameter of the device in order to achieve a predetermined value for another parameter.
Often in integrated circuit (IC) testing a first parameter is adjusted to achieve a specific value in a second parameter. For example, for a given IC device, the voltage can be adjusted in order to produce a predetermined current and visa-versa. Similarly, as another example, the voltage of one component of the integrated circuit device can be adjusted in order to produce a predetermined voltage in another component; the same is true of current. However, the relationship between two parameters can be non-linear and can vary based on other parameters of a given IC device. For example, the transistor characteristics can change on a wafer-by-wafer basis. As a result, it is difficult to have one algorithm that satisfactorily handles multiple adjustments.
Previous attempts to adjust a first parameter, in order to produce a specific value in a second parameter when applied to an IC device, have involved either tailoring or customizing several algorithms for several adjustments, or using only one algorithm to handle multiple adjustments with many iterations. For example, an adjustment where the two parameters are related exponentially, such as the forward voltage versus forward current of a diode, can be accomplished by taking the log of the voltage and applying a linear interpolation/extrapolation to the relationship of the current to the log of voltage. If the two parameters have a square law relationship, it is beneficial to take the log of both parameters and apply a linear interpolation/extrapolation. In each of these cases, the resulting method will work well only for that specific case, since the method is tailored to the relationship between the parameters. These types of methods require more engineering time since the relationship must be coded into the software along with error trapping and other overhead. An adjustment routine made for an exponential will not adjust a square law relationship and visa versa. Both the expediential and square law routines will not handle a linear relationship adequately. The practice of tailoring the routine also requires a priori knowledge of the relationship between the parameters.
Therefore, there is a need for an adjustment algorithm which can handle a variety of adjustments between two related parameters.
In accordance with an exemplary embodiment of the invention, an adjustment algorithm is provided for testing components of a device. The adjustment algorithm modifies itself to adjust a first parameter of a selected device component based on a second parameter of the selected device component which is set to a predetermined value. In addition, the first parameter has a predetermined tolerance. The adjustment algorithm includes the steps of:
(1) obtaining a high limit for the first parameter, a low limit for the first parameter, a high measurement for the second parameter and a low measurement for the second parameter from a prior implementation of the adjustment algorithm to another device component;
(2) applying the first parameter test value to the integrated circuit and measuring the resulting value for the second parameter;
(3) calculating a first parameter error by the algorithm (the second parameter predetermined valuexe2x80x94the second parameter resulting value) * (the first parameter high limitxe2x80x94the first parameter low limit)/(the second parameter high measurementxe2x80x94the second parameter low measurement);
where the first parameter error is less than the tolerance;
(4) setting the first parameter test value to an adjusted value for the first parameter, whereby the first parameter adjusted value generally approximates the second parameter predetermined value when the first parameter adjusted value is applied to the integrated circuit and the second parameter is measured; and
(5) where the first parameter error is one of greater than and equal to the tolerance, calculating an adjusted value for the first parameter by the algorithm (the first parameter test value+the first parameter error)/an algorithm factor, where the algorithm factor is a positive number of at least 1.
In one embodiment according to the invention, each of the IC devices on a wafer, for example, a laser driver, are tested to determine a first parameter (e.g., voltage) which produces a predetermined second parameter (e.g., current). The predetermined current can be dependent upon operating characteristics of the wafer, operating specifications for use of the wafer, etc. Adjustment of the voltage is accomplished by the adjustment algorithm of the present invention. The adjustment algorithm initially assumes a linear relationship between the voltage and current. A voltage error calculated from the linear assumption is divided by an algorithm factor. An algorithm factor of 1 produces an adjustment based on the linear interpolation of the relationship between the voltage and the current. Increasing the value of the algorithm factor causes the algorithm to step across the adjustment range for the voltage using small steps. In the limit, a large value of the algorithm factor will cause the step size to be the smallest possible with the hardware used. Larger values for the algorithm factor can be useful with extremely nonlinear relationships. Moreover, for executions of the algorithm subsequent to its application to the initial IC device or set-up device, the algorithm uses values resulting from an application to a previous IC device. In this way, multiple applications of the algorithm increase its efficiency based on the use of values that have been successful for earlier applications. This artificial intelligence aspect of the algorithm according to the present invention reduces the time necessary to adjust the voltage to yield the predetermined current for subsequent IC devices on the wafer. In the embodiment of the invention, an optimization process calls the adjustment algorithm with different values of the algorithm factor. For the initial application of the algorithm, the algorithm factors can be determined empirically or independently of any testing of the wafer or IC devices contained thereon. In addition, a quality factor is calculated for each algorithm factor. It is desirable that the quality factor be a number having a value which expresses desirable attributes of the adjustment. It is preferable that the adjustment of the parameters be both fast and accurate. Therefore, in one embodiment, the method of calculating the quality factor is the number of iterations multiplied by the quantity of the final error summed with a constant. The resulting quality factor is a number such that the lower the value of the number, the more desirable the adjustment. The purpose of the constant added to the error is to prevent adjustments with zero error and different numbers of iterations yielding the same quality factor. In cases of zero error, it is clear that the lower number of iterations is preferable. Persons of ordinary skill in the art will appreciate that the choice of method of determining the quality factor does not limit the scope of this invention. The value of quality factor should preferably represent the desirability of the adjustment performed. In addition, in the preferred embodiment, the quality factor can either increase with increasing desirability or decrease with increasing desirability. This choice is arbitrary and does not limit the scope of the invention. A learning array stores the parameters being adjusted, the algorithm factors and the corresponding quality factors. For applications of the adjustment algorithm to subsequent IC devices on the wafer, the algorithm factor with the optimal quality factor can be used as a starting point. As a result, like the algorithm, the process uses a value, i.e., an algorithm factor, resulting from successful testing of prior IC devices on the wafer, thereby improving its efficiency. This artificial intelligence aspect of the process according to the embodiment of the invention reduces the time necessary to adjust the voltage to yield the predetermined current for subsequent IC devices on the wafer.
In addition, as the algorithm factor is varied, it has the effect of changing the behavior of the adjustment algorithm. More particularly, the adjustment algorithm is adaptable based on the optimized algorithm factor to implement a previously successful relationship between the voltage and current such that the number of iterations to arrive at the adjusted voltage yielding the predetermined current is minimized. Thus, the algorithm automatically adapts to deal with different relationships between the two parameters. Also, since different adjustment relationships between wafers are common based on transistor characteristics for a given wafer, the adjustment algorithm readily adapts itself for efficient adjustment.
Therefore, the embodiment of the invention is an adjustment algorithm which can handle a variety of adjustments and thereby overcome the problems of known approaches.